module top #(
           parameter count = 100
       )(
           input clk,
           input rst_n,
           input cnt_en,
           output reg [6: 0] out
       );

reg flag;

always@(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
			begin
				out <= 7'd0;
				flag <= 1'b0;
			end
		else if (cnt_en)
			begin
				//写法1
				if (out != count)
					begin
						out <= out + 1'b1;
						flag <= 1'b0;
					end
				else
					begin
						out <= 7'd0;
						flag <= 1'b1;
					end

				//写法2
				if (out == count - 1)
					begin
						out <= 7'd0;
						flag <= 1'b0;
					end
				else
					begin
						out <= out + 1'b1;
						flag <= 1'b0;
					end
			end
	end

endmodule
